By S. Takagi (auth.), Dr. Athanasios Dimoulas, Evgeni Gusev, Professor Paul C. McIntyre, Professor Marc Heyns (eds.)
Will nanoelectronic units proceed to scale in keeping with Moore’s legislations? At this second, there's no effortless solution in view that gate scaling is speedily rising as a significant roadblock for the evolution of CMOS know-how. Channel engineering according to high-mobility semiconductor fabrics (e.g. strained Si, replacement orientation substrates, Ge or III-V compounds) may perhaps support triumph over the stumbling blocks on the grounds that they give functionality enhancement. There are numerous matters even though. can we understand how to make advanced engineered substrates (e.g. Germanium-on-Insulator)? that are the easiest interface passivation methodologies and (high-k) gate dielectrics on Ge and III-V compounds? do we strategy those fabrics in brief channel transistors utilizing flows, toolsets and understand how just like that during Si expertise? How do those fabrics and units behave on the nanoscale? The reader gets a transparent view of what has been performed to date, what's the state of the art and that are the most demanding situations forward sooner than we come any just about a doable Ge and III-V MOS technology.
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