By Marshall C. Yovits
Includes long assessment articles on laptop aided good judgment synthesis for VLSI chips, sensor-driven clever robotics, complicated innovations in dealing with disbursed facts, details move and regulate among people and pcs and automated balloting.
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Additional info for Advances in Computers, Vol. 32
Usually there is more than one permissible function for each of vi and cii. But when we find a set of permissible functions for a gate or connection, all the vectors representing these permissible functions can be expressed by one vector as discussed in the following. This is convenient for processing. For example, suppose the output function f ( u i )of a gate vi in a network has the values shown in the column labeled f(ui) in the truth table in Table 11, where the network has input variables xl, x2,.
1977), the root node represents the network that consists of only m output gates whose outputs realize the given m functions. Each time a new gate, one of the existing gates, or an external variable is connected to an input of some gate, we branch to a node on a next low level on the tree. When a network thus constructed by repeating branching realizes the given m functions, it represents a terminal node, from which the tree does not branch further. Among networks derived at such terminal nodes, a minimal network can be found.
So, even with this highly specialized program, we are unable to design minimal networks consisting of more than about ten NOR gates in a reasonable time except for special cases. 9. Processing time. 3 Logic Networks Designed Minimal NOR gate networks were designed for some functions of a few variables and also it was verified, at least with small networks, that when the number of NOR gates is reduced, the number of connections tends to be reduced (Muroga and Lai, 1976). For the majority of a few hundred functions tested, networks designed with a minimum number of NOR gates as the primary objective and with a minimum number of connections as the secondary objective are completely identical to those designed with a minimum number of connections as the primary objective and with a minimum number of gates as the secondary objective.