Download Design of high-performance microprocessor circuits by Anantha Chandrakasan, William J. Bowhill, Frank Fox PDF

By Anantha Chandrakasan, William J. Bowhill, Frank Fox

Bankruptcy 1 effect of actual expertise on structure / John H. Edmondson three -- half II expertise concerns 25 -- bankruptcy 2 CMOS Scaling and matters in Sub-0.25 [mu]m platforms / Yuan Taur 27 -- bankruptcy three strategies for Leakage strength aid / Vivek De, Yibin Ye, Ali Keshavarzi, Siva Narendra, James Kao, Dinesh Somasekhar, Raj Nair, Shekhar Borkar forty six -- bankruptcy four Low-Voltage applied sciences / Tadahiro Kuroda, Takayasu Sakurai sixty three -- bankruptcy five Soi expertise and Circuits / Ghavam G. Shahidi, Fari Assaderaghi, Dimitri Antoniadis eighty -- bankruptcy 6 types of method adaptations in gadget and Interconnect / Duane Boning, Sani Nassif ninety eight -- half III Circuit types for good judgment 117 -- bankruptcy 7 uncomplicated common sense households / Kerry Bernstein 119 -- bankruptcy eight concerns in Dynamic common sense layout / Paul Gronowski one hundred forty -- bankruptcy nine Self-Timed Pipelines / Ted Williams 158 -- bankruptcy 10 High-Speed VLSI Airthmetic devices: Adders and Multipliers / Vojin G. Oklobdzija 181 -- half IV Clocking 205 -- bankruptcy eleven Clocked garage parts / Hamid Partovi 207 -- bankruptcy 12 layout of High-Speed CMOS PLLs and DLLs / John George Maneatis 235 -- bankruptcy thirteen Clock Distribution / Daniel W. Bailey 261 -- half V reminiscence method layout 283 -- bankruptcy 14 sign up records and Chahes / Ronald Preston 285 -- bankruptcy 15 Embedded Dram / Tadaaki Yamauchi, Michihiro Yamada 309 -- half VI Interconnect and I/O 329 -- bankruptcy sixteen studying on-Chip Interconnect results / Noel Menezes, Lawrence Pileggi 331 -- bankruptcy 17 concepts for riding Interconnect / Shannon V. Morton 352 -- bankruptcy 18 I/O and ESD Circuit layout / Stephen C. Thierauf, Warren R. Anderson 377 -- bankruptcy 19 High-Speed electric Signaling / Stefanos Sidiropoulos, Chih-Kong Ken Yang, Mark Horowitz 397 -- half VII Reliability 427 -- bankruptcy 20 Electromigration Reliability / J. Joseph Clement 429 -- bankruptcy 21 scorching service Reliability / Kaizad Mistry 449 -- half VIII Cad instruments and try out 467 -- bankruptcy 22 evaluation of Computer-Aided layout instruments / Yao-Tsung Yen 469 -- bankruptcy 23 Timing Verification / Victor Peng 480 -- bankruptcy 24 layout and research of strength Distribution Networks / David Blaauw, Rajendran Panda, Rajat Chaudhry 499 -- bankruptcy 25 checking out of High-Performance Processors / Dilip okay. Bhavsar 523

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7 Conclusion The present trend to scale technology for high-performance processors to smaller and smaller dimensions without reducing power supply voltage is difficult to sustain due to increasing power density and current density. Operating at lower voltage would offer relief for these problems and much lower energy per computation, but the principal challenge to this is threshold variability. The ultimate silicon device may be one that minimizes VT variability and/or allows adaptive control to adjust VT to the optimum level.

27] and Baker [28]. 3 Going Beyond FEOL Scaling Limits Gate Scaling Gate scaling and materials for the gates provide one of the greatest challenges to front-end scaling. To tackle the challenges, gates with high k (in order to keep the thickness higher) will involve the use of newer materials: these may include rare-earth oxides. New gate structures have been introduced: Tri-Gate (Intel) and metallic gates (IBM). Strain Engineering for Enhancing Mobility In order to offset the degradation in performance due to the decrease in the gate length (a consequence of scaling), some companies have shown the use of strained channel to increase the mobility of carriers.

There is a growing feeling among the research community that new gates and gate materials will have to be invented to mitigate gate leakage effects. There are many electric and manufacturing and electrical issues with extremely thin gates. Gate leakage is one of the main limiters (see Ref. 1). 6). See also Ref. [49]. 1 Role of Lithography It will be obvious to the reader that lithography must play a central role in device scaling. There are many excellent references and books that deal with this subject.

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