Download FinFETs and Other Multi-Gate Transistors by J.-P. Colinge PDF

By J.-P. Colinge

This ebook explains the physics and homes of multi-gate field-effect transistors (MuGFETs), how they're made and the way circuit designers can use them to enhance the performances of built-in circuits. It covers the emergence of quantum results because of the decreased dimension of the units and describes the evolution of the MOS transistor from classical constructions to SOI (silicon-on-insulator) after which to MuGFETs.

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Extra info for FinFETs and Other Multi-Gate Transistors

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E. Y. Nguyen, J. Mogab: CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET). C. Lemme, T. Mollenhauer, W. Henschel, T. Wahlbrink, M. Baus, O. Winkler, R. Granzner, F. Schwierz, B. Spangenberg and H. Kurz: Subthreshold behavior of triple-gate MOSFETs on SOI Material. Solid State Electronics 48-4, 529 (2004) X. P. Colinge, V. Bayot, E. Grivei: Quantum-wire effects in thin and narrow SOI MOSFETs. P. Colinge, X. Baie, V. Bayot, E. Grivei: A silicon-on-insulator quantum wire. Solid-State Electronics 39, 49 (1996) R.

They are not part of intrinsic device operation and they can usually be eliminated by increasing the doping concentration in the corners. In a multigate device, on the other hand, the corners are part of the intrinsic transistor structure. 16. The thickness and width of the device are tsi and Wsi, and the radius of curvature of the top and the bottom corners is noted rtop and rbot, respectively. The gate oxide thickness is 2 nm, and tsi=Wsi=30 nm. Because the gate material is N+ polysilicon, high doping concentrations have to be used to achieve useful threshold voltage values (N-channel device).

Van de Wiele: Modeling of ultrathin double-gate nMOS-SOI transistors. Solid-State Electronics 41-5, 715 (1994) 113 A. Terao, D. Flandre, E. Lora-Tamayo, F. Van de Wiele, IEEE Electron Device Letters, 12-12, 682 (1991) 114 E. Rauly, B. Iñiguez, D. Flandre, C. Raynaud: Investigation of single and double gate SOI MOSFETs in Accumulation Mode for enhanced performances and reduced technological drawbacks. Proceedings of ESSDERC, 540 (2000) 115 W. W. P. Colinge: Corner effect in multiple-gate SOI MOSFETs.

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