Download Low-Voltage SOI CMOS VLSI Devices and Circuits by James B. Kuo PDF

By James B. Kuo

A pragmatic, complete survey of SOI CMOS units and circuits for microelectronics engineers
The microelectronics is changing into more and more depending on SOI CMOS VLSI units and circuits. This booklet is the 1st to handle this significant subject with a pragmatic specialize in units and circuits. It presents an up to date survey of the present wisdom concerning SOI machine behaviors and describes cutting-edge low-voltage CMOS VLSI analog and electronic circuit techniques.
Low-Voltage SOI CMOS VLSI units and Circuits covers the total box, from easy recommendations to the main complex rules. themes include:
* SOI machine habit: primary and floating physique results, scorching provider results, sensitivity, reliability, self-heating, breakdown, ESD, dual-gate units, accumulation-mode units, brief channel results, and slim channel effects
* Low-voltage SOI electronic circuits: floating physique results, DRAM, SRAM, static good judgment, dynamic common sense, gate array, CPU, frequency divider, and DSP
* Low-voltage SOI analog circuits: op amps, filters, ADC/DAC, sigma-delta modulators, RF circuits, VCO, mixers, low-noise amplifiers, and high-temperature circuits
With over three hundred references to the cutting-edge and over three hundred vital figures on low-voltage SOI CMOS units and circuits, this quantity serves as an authoritative, trustworthy source for engineers designing those circuits in high-tech industries.

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Sample text

As shown in Fig. 40 elective electron motility versus the vertical electric field for several substrate concentrations. ) mobility is degradeddue to surface scattering. Only under a small vertical electric field is the mobility sensitiveto the variation in the doping density of the thin film. As shownin Fig. 4 1(b), both bulk and SOI devicesdemonstrateabout identical mobility characteristics. As indicated in this figure, a variation in the thin-film thicknessdoes not lead to any significant difference in the mobility characte~stics.

0 Channel Lc&th (p m) Fig. 19 Threshold voltage versus channel length of an FD SOI NMOS device with a front gate oxide of 50 A, a thin film of 1000 A, and a buried oxide of 4200 A, using polysilicon and tantalum gates. (Adapted from Ushiki et al. I 1 10 Gate Voltage VG -A&B (V) Channel Length (p m) (a) 04 Fig. 20 (a) Capacitance-voltage characteristics of the FD SO1 PMOS device with a front gate oxide of 40 h, a thin film of 500 A, and using TiN and polysilicon gates. I and using the TiN gate.

Thus, its subt~esl~oldslopemay be different. At a negative back gate bias, the device tendsto be PD. Under this situation, its threshold voltage is less influenced by the back gate bias (VSUB). On the other hand, at a positive back gate bias (VS~JB),this device becomesFD, which meansits thin film is fully depleted. 5ym 1O-6 - 3 z lo-" i! -t 10‘8' 2 1o-g- lo-'*- Gate Voltage (V) Fig. I implanted with p-type dopants with a dose of 4 x 1012cme2, biased at various back gate biases. (Adapted from Wang et al.

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