By George E. Anner (auth.)
Planar Processing Primer relies on lecture notes for a silicon planar technique ing lecture/lab path provided on the college of Illinois-UC for over fifteen years. Directed essentially to electric engineering upperclassmen and graduate scholars, the cloth additionally has been used effectively via graduate scholars in physics and ceramic and metallurgical engineering. it really is compatible for self-study by way of engineers educated in different disciplines who're starting paintings within the semiconductor fields, and it may possibly make circuit layout engineers conscious of the processing barriers less than which they have to paintings. The textual content describes and explains, at an introductory point, the crucial processing steps used to transform uncooked silicon right into a semiconductor gadget or built-in circuit. First-order versions are used for theoretical remedies (e.g., of diffusion and ion implantation), in regards made to extra complicated remedies, to machine courses comparable to SUPREM that come with larger order results, and to interactions between sequential methods. In Chapters eight, nine, and to, the appliance of silicon approaches to compound semiconductors is mentioned in brief. over the last a number of years, the dimensions of transistors has lowered markedly, permitting extra transistors in step with chip unit region, and chip measurement has increased.
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The final assembly step involves closing and sealing the body of the package. The actual processes that are required depend upon the type of package being used. The hermetically sealed types require placement of a lid or cap, which then is welded or soldered to the main body under vacuum. For the more common rectangular plastic types, the metal lead frame is inserted into a hot-molding press and plastic is injected. This is then pressed to shape and cured to form the body around the chip. Packages of this general shape with up to 50 external leads have been used.
The required masking thickness depends on the dopant species, the mask material, and the ion beam energy. For very high energy implants the masking properties of Si02 are augmented by an overlayer of a heavy metal such as gold, platinum, tungsten, or tantalum. Silicon nitride and photoresist also may be used as implant masks. , at different rates). For example, for mask windows the etch must attack Si02 but not Si and PR; to delineate connects in an Al layer it must attack Al but not PR, Si02 or Si 3 N 4 • Fortunately, selective etches are available in both liquid and gas form for these and other material combinations.
The wafer is exposed to a selective etch that cuts windows in the Si02 without affecting the PR and underlying silicon. Window positions coincide in the oxide and PRo 7. The PR, having served its purpose, is removed by a stripping process. The exposed, windowed oxide layer then is ready to serve as a mask for diffusion or 12. The dopant atoms can pass only through the windows and so delineate the doped regions in the Si wafer. Note that the horizontal geometry and locations of the doped areas ultimately are determined by the pattern on the original photomask.