Download Power Management of Digital Circuits in Deep Sub-Micron CMOS by Stephan Henzler PDF

By Stephan Henzler

In the deep sub-micron regime, the facility intake has turn into the most vital matters for aggressive layout of electronic circuits. because of dramatically expanding leakage currents, the ability intake doesn't make the most of know-how scaling as earlier than. State-of-art strength relief thoughts just like the use of a number of provide and threshold voltages, transistor stack forcing and tool gating are mentioned with recognize to implementation and gear saving potential. concentration is given specifically on know-how dependencies, strategy adaptations and expertise scaling. layout and implementation matters are mentioned with recognize to the trade-off among energy relief, functionality degradation, and approach point constraints. a whole top-down layout move is verified for strength gating strategies introducing new layout methodologies for the change sizing activity and circuit blocks for data-retention and block activation. The leakage relief ratio and the minimal power-down time are brought as figures of benefit to explain the facility gating approach on process point and provides a relation to actual circuit parameters. Power administration of electronic Circuits in Deep Sub-Micron CMOS Technologies in general bargains with circuit layout but additionally addresses the interface among circuit and approach point layout at the one part and among circuit and actual layout at the different part.

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One drawback of the pass gate level-converter is the fact that still both supply voltages are required: Even without the input inverter, the VDD,low potential is needed at the gate of the pass gate device. This results in all the design related overhead which has been discussed above for the standard level-converter. Another drawback is the restriction VDD,low ≤ VDD,high . If the VDD,low potential is significantly larger than VDD,high the pass transistor turns on and there is a direct current path from the high output of the input inverter to the VDD,high supply.

The third distribution is a typical case for random logic. In the second case, it may be worthwhile to inspect the reason for the large number of critical paths. In datapath circuits, the regular signal processing structure results in many parallel critical paths, and the multi-VDD approach is not useful. A distribution like case 2 can also be the result of a timing driven place and route tool with power optimization. This is because these tools reduce the size of transistors in non-critical paths in order to reduce dynamic losses.

A waste of power not related to the timing slack are logically active circuit blocks which do not contribute to the functionality of the system. The clock of such circuit blocks can be turned off to avoid switching activity and power consumption within these blocks. This clock gating technique can lower the dynamic power consumption of a chip significantly. In an unused circuit block the inputs normally do not change. Thus the dynamic power consumption of this block is determined by the clock tree and the flipflops.

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