By Fred K. Manasse
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Extra info for Semiconductor Electronics Design
Floorplanning is a critical step, as it sets up the ground work for a good layout. All modules are given a place (or often a region) in the chip without considering all details, such as the orientation or the exact shape of the module. During placement, the modules are exactly positioned on the chip. The goal of placement is to find a minimum area arrangement for the modules that allows completion of interconnections between modules, while meeting the performance constraints. Placement is typically done in two phases.
N. Sherwani ([She97], p. xvii) Wire length estimates for improving the circuit layout are also very useful for automatic CAD. Moreover, they form a supplementary challenge for the future since future CAD tools for automatic design should be able to choose priorities that are clear to a designer's 'insight' in the design. This is not only beneficial for the system's speed, but, for a fixed calculation time, also the quality of the solution. The importance of a priori wire length distributions for the performance of CAD tools has not always been recognized by the research community.
The importance of a priori wire length distributions for the performance of CAD tools has not always been recognized by the research community. This might explain the fact that very little additional research work has been done since the pioneering works of Rent and especially Donath, at the end of the 70's. The increasing demands put on CAD tools and the ever more important influence of the interconnection structure on the circuit performance make researchers realize that parameter estimation, especially wire length estimation, should become am important research domain.