Download ULSI semiconductor technology atlas by Chih-Hang Tung PDF

By Chih-Hang Tung

Greater than 1,100 TEM photos illustrate the technological know-how of ULSI

The common outgrowth of VLSI (Very huge Scale Integration), extremely huge Scale Integration (ULSI) refers to semiconductor chips with greater than 10 million units in step with chip. Written by means of 3 well known pioneers of their box, ULSI Semiconductor know-how Atlas makes use of examples and TEM (Transmission Electron Microscopy) micrographs to give an explanation for and illustrate ULSI procedure applied sciences and their linked problems.

the 1st ebook on hand at the topic to be illustrated utilizing TEM pictures, ULSI Semiconductor expertise Atlas is logically divided into 4 parts:
* half I contains simple introductions to the ULSI method, machine building research, and TEM pattern practise
* half II specializes in key ULSI modules--ion implantation and defects, dielectrics and isolation buildings, silicides/salicides, and metallization
* half III examines built-in units, together with whole planar DRAM, stacked telephone DRAM, and trench mobile DRAM, in addition to SRAM as examples for technique integration and improvement
* half IV emphasizes specified functions, together with TEM in complex failure research, TEM in complicated packaging improvement and UBM (Under Bump Metallization) stories, and high-resolution TEM in microelectronics

This cutting edge consultant additionally presents engineers and executives within the microelectronics undefined, in addition to graduate scholars, with:
* greater than 1,100 TEM photographs to demonstrate the technology of ULSI
* A ancient creation to the know-how in addition to assurance of the evolution of easy ULSI procedure difficulties and issues
* dialogue of TEM in different complicated microelectronics units and fabrics, corresponding to flash thoughts, SOI, SiGe units, MEMS, and CD-ROMs

Show description

Read Online or Download ULSI semiconductor technology atlas PDF

Similar semiconductors books

Printed Circuits Handbook (McGraw Hill Handbooks)

The World's number 1 advisor to published Circuit Boards_Now thoroughly up to date with the most recent details on Lead-Free production! the simplest reference within the box for over 30 years, the published Circuits guide equips you with definitive insurance of each side of published circuit assemblies_from layout how you can fabrication tactics.

Power-Switching Converters, Second Edition (Electrical Engineering and Electronics)

After approximately a decade of good fortune because of its thorough assurance, abundance of difficulties and examples, and functional use of simulation and layout, Power-Switching Converters enters its moment variation with new and up-to-date fabric, fullyyt new layout case reviews, and improved figures, equations, and homework difficulties.

Technology of Bottled Water, Second Edition

The bottled waters has turn into an important and full of life area of the beverage international, in constructed and constructing nations around the world. on account that e-book of the 1st variation in 1998, the has passed through a notable enlargement, and this has served to underline the necessity for an obtainable resource of technical tips.

Extra info for ULSI semiconductor technology atlas

Example text

REFERENCES R. Alani and R. J. Mitro, Proc. 25th Int. Symp. Testing and Failure Analysis, 439–448, 1999. P. Auger, J. Phys. , 6, 205, 1925. W. E. Beadle, J. C. Tsai, and R. D. Plummer, Quick Reference Manual for Silicon Integrated Circuit Technology, Wiley, 1985. G. Binning, H. Rohrer, Ch. Gerber, and E. Weibel, App. Phy. , 40, 178, 1982. B. Brar, G. J. Sullivan, and P. M. Asbeck, IEEE Trans. Electron Devices, 48 (11), 2473–2476, 2001. A. Briggs, Acoustic Microscopy, Clarendon Press, 1992. P. R.

Vac. Sci. , A18 (4), 1–13, 2000. C. Yang, 50 Years of Electron Devices: The IEEE Electron Devices Society and Its Technologies, 1952–2002. IEEE, 2002, foreword. 2 ULSI Process Technology 50 nm Misaligned 4-poly stacked capacitor DRAM cell. TEM cross section image resembles a horse head. The ultra (very) large silicon integrated (ULSI/VLSI) circuits wafer process technology is a dynamically changing and living entity. Even in the mass production environment where process stability and repeatability are basic requirements, minor modifications happen very often and major technology revolves monthly or quarterly.

CMP to Remove Excess CVD Oxide (Fig. 7). Chemical mechanical polishing (CMP) is used to remove excess CVD oxide with SiN used as the stopper. As the CMP excess oxide stops on application of SiN, a somewhat planar profile is produced. Wide and narrow features have different starting topographies and complicate the CMP process. Some assistance can result from adding “dummy” (nonfunctional) active features to wide STI trenches or using extra mask plus partial oxide etch of the “highest” regions before CMP.

Download PDF sample

Rated 4.29 of 5 – based on 29 votes